CPE 351 - Digital Systems Design with VHDL

2 Unit(s)

Finite State Machine: definition, Mealy and Moore models, state diagram, state table, transition table. Sequential circuits design using flip-flops, asynchronous, and synchronous circuit design. Algorithm State Machine. Design examples and exercises. Structured Design; Computer-aided electronic system design tools, Schematic circuit capture, Hardware description languages, Design process (simulation, synthesis), Structural design decomposition. Introduction to VHDL: VHDL language abstractions, Design hierarchies, VHDL component, Lexical description, VHDL source file, Data types, Data objects, Language statements, Concurrent VHDL, Sequential VHDL, Advanced features of VHDL (library, package and subprograms). Structural level modelling, Register-Transfer level modelling, FSM with datapath level modelling, Algorithmic level modelling. Introduction of ASIC, Types of ASIC, ASIC design process, Standard cell ASIC synthesis, FPGA Design Paradigm, FPGA synthesis, FPGA/CPLD Architectures. VHDL Designs.