CPE 553 - Embedded Systems Design

3 Unit(s)

Structural level modelling, Register-Transfer level modelling, FSM with data path level modelling, Algorithmic level modelling. Introduction of ASICs, Types of ASICs, ASIC design process, Standard cell ASIC synthesis. FPGA Design Paradigm, FPGA synthesis, FPGA/CPLD Architectures. VHDL Design: Top-down design flow, Verification, Writing RTL VHDL code for synthesis, top-down design with FPGA. VHDL synthesis, Optimization and mapping, constraints, technology library, delay calculation, synthesis tool, synthesis directives. Computer-aided design of logic circuits.